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Espressif Systems /ESP32-C2 /UART0 /CONF1

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Interpret as CONF1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RXFIFO_FULL_THRHD0TXFIFO_EMPTY_THRHD0 (DIS_RX_DAT_OVF)DIS_RX_DAT_OVF 0 (RX_TOUT_FLOW_DIS)RX_TOUT_FLOW_DIS 0 (RX_FLOW_EN)RX_FLOW_EN 0 (RX_TOUT_EN)RX_TOUT_EN

Description

Configuration register 1

Fields

RXFIFO_FULL_THRHD

It will produce rxfifo_full_int interrupt when receiver receives more data than this register value.
TXFIFO_EMPTY_THRHD

It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.
DIS_RX_DAT_OVF

Disable UART Rx data overflow detect.
RX_TOUT_FLOW_DIS

Set this bit to stop accumulating idle_cnt when hardware flow control works.
RX_FLOW_EN

This is the flow enable bit for UART receiver.
RX_TOUT_EN

This is the enble bit for uart receiver’s timeout function.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data